Correct. Goal is to emulate the SIDs, and the filters are analog, so analog simulation is required.

FPGAs are good fun, and some of the stuff I’m working on in particular gets even crazier. My current project is emulating a partially analog soundchip (the 6581 and 8580 SIDs) with 32 bit integers, because FPGAs can’t do analog. The best part is, it actually (mostly) works. Still have coefficient issues with the RC circuits, and the Rf1 and Rf2 voltage-controlled resistor coefficient tables need to be recalculated, but it’s already looking pretty good.

Good fun lol

Aa far as I’m aware, incremental synthesis is vivado trying to build a new FPGA bitstream by modifying a snapshot of the previous build, to ostensibly save time. Because the SID FPGA implementation is a relatively small part of the MEGA65 core, it really likes to forget to add any changes I make, especially related to timing optimization (it took me so long to figure out it had re-enabled itself, after disabling it my total negative slack was cut in half due to it finally registering all the pipelining and other optimization). I’ve also had vivado outright lock up with some cases.

Do repos on GitHub and assorted messages on text-based communication platforms count as content? Because if that’s the case, then all the time, because I generally write stuff down in case I proceed to forget exactly what that function did or why I calculated this bypass coefficient like this or why for the love of fuck does vivado keep reverting to incremental synthesis and how did I fix it last time aaaaaaaaaaaaaaaaaaaaaaaa

As for if my random technical nonsense has any bearing on the world, not really, outside of maaaybe the demoscene if the SID stuff works out, and the few people who like reading my ramblings for some reason.

https://alliancespaceguard.com, pretty much daily. Can’t wait for it to release.

This one on lemmy.today, and my original account with the same username on lemmy.world.